1. Field of the Invention
This invention generally relates to a clock signal amplifying method and driving stage for liquid crystal display (LCD) driving circuit, and more particularly to a clock signal amplifying method and driving stage for liquid crystal display (LCD) driving circuit that exerts low power consumption and stable performance.
2. Description of Related Art
To follow up modern lifestyle, video or image apparatus comes up with lightness and miniature. A conventional Cathode Ray Tube (CRT) partially shares advantages, yet it is voluminous due to the electronic gun feature. On the other hand, it takes too much space and as well as causes radiant problem. Therefore, the main stream of flat panel display is to integrate optoelectronics and semiconductor technologies for developing Liquid Crystal Display (LCD), Organic Light-Emitting Diodes (OLED) Display, or Plasma Display Panel (PDP).
Wherein the flat panel display field, an image of the LCD is composed of a plurality of pixels, arranging in a array, and the luminance of each of the pixels is controlled by both lightness of back-light module and grayscale. In a present driving method for LCD, the most common driving method is to keep a constant luminance of the back light module, and twist the crystal of each pixel by a bias voltage according to image information. Light transmittance is thereby determined with crystal twist angle, so as to display various grayscale.
A Thin Film Transistor (TFT) is a broad application device for LCD, for conducting or cut-off current. The driving circuit for the TFT display is to receive an image data, and hold the sampled image data for each of the pixels corresponding to LCD within a horizontal period. Thereafter, the driving circuit outputs a whole batch of image data at beginning or halfway of next horizontal period.
Referring to FIG. 1, it is a block diagram illustrating a conventional LCD driving circuit, where each driving stage includes a shift register 105, a level shifter 110, and an output buffer 115. Wherein the level shifter 110 is coupled to the shift register 105 and the output buffer 115. The clock signal of the shift register 105 swings between VDD (10V, for example) and GND. Since the shift register 105 operates at VDD and GND, whereas the level shifter 110 and the output buffer 115 operates at VDD and VSS, where VSS is negative voltage level. Therefore, the driving stage in conventional scheme relatively is power consuming on the clock propagation line due to a large clock swing.
Referring to FIG. 2A, it is a block diagram illustrating a driving stage of a conventional LCD driving circuit. The driving stage includes a first level shifter 203, a shift register 206, a second level shifter 209, and an output buffer 212. Wherein, the shifter register 206 couples the first shift register 203 to the second shift register 209. The output buffer 212 is coupled to the second shift register 209. The clock signal for the first level shifter 203 swings between a small range, between 3V and GND, for example. Referring to FIG. 2B, it is a diagram illustrating level shifting of a conventional LCD driving circuit. In the conventional scheme, the first level shifter 203 and the shift register 206 operates at VDD and GND for shifting 3V voltage level to VDD. The second level shifter 209 and the output buffer 212 operates at VDD and VSS for shifting GND to VSS level. According to a formula for dynamic power consumption: P=fcV2, it is noted that power is in proportion to square of voltage level, wherein P is power consumption, f is operating frequency, c is loading capacitance, and V is signal amplitude. Therefore, this second conventional circuit consumes less power on the clock propagation line than the first convention circuit in foregoing description.